Integration challenges of 0.1μm CMOS Cu/low-k interconnects

被引：15

作者：

Yu, KC ^{[1
]}

Werking, J ^{[1
]}

Prindle, C ^{[1
]}

Kiene, M ^{[1
]}

Ng, MF ^{[1
]}

Wilson, B ^{[1
]}

Singhal, A ^{[1
]}

Stephens, T ^{[1
]}

Huang, F ^{[1
]}

Sparks, T ^{[1
]}

Aminpur, M ^{[1
]}

Linville, J ^{[1
]}

Denning, D ^{[1
]}

Brennan, B ^{[1
]}

Shahvandi, I ^{[1
]}

Wang, C ^{[1
]}

Flake, J ^{[1
]}

Chowdhury, R ^{[1
]}

Svedberg, L ^{[1
]}

Solomentsev, Y ^{[1
]}

Kim, S ^{[1
]}

Cooper, K ^{[1
]}

Usmani, S ^{[1
]}

Smith, D ^{[1
]}

Olivares, M ^{[1
]}

Carter, R ^{[1
]}

Eggenstein, B ^{[1
]}

Strozewski, K ^{[1
]}

Junker, K ^{[1
]}

Goldberg, C ^{[1
]}

Filipiak, S ^{[1
]}

Martin, J ^{[1
]}

Grove, N ^{[1
]}

Ramani, N ^{[1
]}

Ryan, T ^{[1
]}

Mueller, J ^{[1
]}

Guvenilir, A ^{[1
]}

Zhang, D ^{[1
]}

Ventzek, P ^{[1
]}

Wang, V ^{[1
]}

Lii, T ^{[1
]}

King, C ^{[1
]}

Crabtree, P ^{[1
]}

Farkas, J ^{[1
]}

Iacoponi, J ^{[1
]}

Pellerin, J ^{[1
]}

Melnick, B ^{[1
]}

Woo, M ^{[1
]}

Weitzman, E ^{[1
]}

机构：

[1] Motorola Inc, Dan Noble Ctr, Digital DNA Labs, AMD Alliance, Austin, TX 78728 USA

来源：

PROCEEDINGS OF THE IEEE 2002 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE | 2002年

关键词：

D O I：

10.1109/IITC.2002.1014870

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The integration challenges of a low-k dielectric (k<3) to form multi-level Cu interconnects for the next generation 0.1mum CMOS technology are presented. Process improvements to overcome these challenges are highlighted which include etchfront control, resist poisoning, high aspect ratio metallization, and improved CMP planarity. The maturity of this technology has been demonstrated through high yield of a 4MB SRAM test vehicle.

引用

页码：9 / 11

页数：3