A hybrid architecture for bioinformatics

被引:8
作者
Schmidt, B
Schröder, H
Schimmler, M
机构
[1] Nanyang Technol Univ, Sch Comp Engn, Singapore 639798, Singapore
[2] Tech Univ Braunschweig, Inst Datentech & Kommunikationsnetze, D-38106 Braunschweig, Germany
来源
FUTURE GENERATION COMPUTER SYSTEMS-THE INTERNATIONAL JOURNAL OF ESCIENCE | 2002年 / 18卷 / 06期
关键词
hybrid parallel architecture; high performance biosequence database searching; Smith-Waterman algorithm; instruction systolic array; cluster computing;
D O I
10.1016/S0167-739X(02)00058-4
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
We present a hybrid parallel system based on commodity components to gain supercomputer power at low cost. The architecture is built around a coarse-grained PC-cluster linked by a high-speed network and fine-grained parallel processor arrays connected to each node. Identifying applications that profit from this kind of processing power is critical to justify the use of such a system. In this paper, we present a new approach to high performance protein database scanning with hybrid computing. To derive an efficient mapping onto this architecture, we designed an instruction systolic sequence comparison algorithm. This results in a database scanning implementation with significant runtime savings. (C) 2002 Elsevier Science B.V. All rights reserved.
引用
收藏
页码:855 / 862
页数:8
相关论文
共 18 条
[1]  
ALTSCHUL SF, 1990, J MOL BIOL, V215, P403, DOI 10.1006/jmbi.1990.9999
[2]  
BORAH M, 1994, P ASAP 94 IEEE CS, P144
[3]  
Dahle D, 1999, INTERNATIONAL CONFERENCE ON PARALLEL AND DISTRIBUTED PROCESSING TECHNIQUES AND APPLICATIONS, VOLS I-V, PROCEEDINGS, P1243
[4]  
GUERDOUXJAMET P, 1997, CABIOS, V12, P609
[5]  
Hoang D. T., 1993, Proceedings IEEE Workshop on FPGAs for Custom Computing Machines (Cat. No.93TH0535-5), P185, DOI 10.1109/FPGA.1993.279464
[6]  
Hughey R, 1996, COMPUT APPL BIOSCI, V12, P473
[7]   THE INSTRUCTION SYSTOLIC ARRAY AND ITS RELATION TO OTHER MODELS OF PARALLEL COMPUTERS [J].
KUNDE, M ;
LANG, HW ;
SCHIMMLER, M ;
SCHMECK, H ;
SCHRODER, H .
PARALLEL COMPUTING, 1988, 7 (01) :25-39
[8]  
LANG HW, 1994, LECT NOTES COMPUTER, V797, P487
[9]  
LANG HW, 1986, VLSI J, V4, P65
[10]  
Lavenier D, 1998, ADV PAR COM, V12, P81