Power-centric design of high-speed I/Os

被引：12

作者：

Hatamkhani, Hamid ^{[1
]}

Lambrecht, Frank ^{[2
]}

Stojanovic, Vladimir ^{[3
]}

Yang, Chih-Kong Ken ^{[4
]}

机构：

[1] Univ Calif Los Angeles, 9 Marisol, Newport Coast, CA 92657 USA

[2] Rambus Inc, Los Altos, CA 94022 USA

[3] MIT, Cambridge, MA 02139 USA

[4] Univ Calif Los Angeles, Los Angeles, CA 90095 USA

来源：

43RD DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 2006 | 2006年

关键词：

algorithms; performance; design; standardization; I/O; Serial Link; Power Minimization; Convex Optimization; Channel Model;

D O I：

10.1109/DAC.2006.229252

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

With increasing aggregate off-chip bandwidths exceeding terabits/second (Tb/s), the power dissipation is a serious design consideration. Additionally, design of I/O links is constrained by a complex set of specifications such as voltage levels, voltage noise, signal deterministic jitter, random jitter, slew rate, BER etc. These specifications lead to complex tradeoffs for both circuits and circuit architecture in order to minimize power. This paper presents a design framework that enables the analysis of tradeoffs in the design of an I/O transmitter. The design framework includes BER analysis with a channel model coupled with logic sizing optimization that is constrained by the desired signaling specification.

引用

页码：867 / +

页数：2