Integrated circuits for data transmission over twisted-pair channels

被引:40
作者
Johns, DA [1 ]
Essig, D [1 ]
机构
[1] BROOKTREE CORP,SAN DIEGO,CA 92121
关键词
clock recovery; digital transmission; echo cancellation; equalization;
D O I
10.1109/4.557638
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This tutorial paper discusses typical architectures and challenges in designing integrated circuits for data transmission over twisted-pair wire channels, To highlight the various architectural approaches, two main applications are discussed-high-bit-rate digital subscriber loop (HDSL) and fast-ethernet, Although these two applications have orders of magnitude difference in their bit rates, they share many common building blocks including line-drivers, 2-4 wire hybrids, echo cancellation, digital equalization, and clock recovery, Typical integrated circuit approaches for realizing each of these blocks are presented as well as possible tradeoffs, Finally, future challenges facing integrated circuit designers are presented.
引用
收藏
页码:398 / 406
页数:9
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