Low standby power CMOS with HfO2 gate oxide for 100-nm generation

被引：28

作者：

Pidin, S ^{[1
]}

Morisaki, Y ^{[1
]}

Sugita, Y ^{[1
]}

Aoyama, T ^{[1
]}

Irino, K ^{[1
]}

Nakamura, T ^{[1
]}

Sugii, T ^{[1
]}

机构：

[1] Fujitsu Labs Ltd, Akiruno, Tokyo 1970833, Japan

来源：

2002 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS | 2002年

关键词：

D O I：

10.1109/VLSIT.2002.1015375

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We have fabricated 55-nm poly-Si gated n- and p-MOSFETs with HfO2 gate dielectric of 3-nm physical thickness deposited by atomic layer deposition (ALD). Conventional CMOS process was used with high-temperature S/D anneal of greater than or equal to1000degreesC, cobalt-silicide and pocket implant. The devices showed very promising characteristics for low standby power applications due to drastic reduction of gate leakage current.

引用

页码：28 / 29

页数：2