A manufacturable Copper/low-k SiOC/SiCN process technology for 90nm-node high performance eDRAM

被引：48

作者：

Higashi, K ^{[1
]}

Nakamura, N ^{[1
]}

Miyajima, H ^{[1
]}

Satoh, S ^{[1
]}

Kojima, A ^{[1
]}

Abe, J ^{[1
]}

Nagahata, K ^{[1
]}

Tatsumi, T ^{[1
]}

Tabuchi, K ^{[1
]}

Hasegawa, T ^{[1
]}

Kawashima, H ^{[1
]}

Arakawa, S ^{[1
]}

Matsunaga, N ^{[1
]}

Shibata, H ^{[1
]}

机构：

[1] Toshiba Co Ltd, Semicond Co, Syst LSI Res & Dev Ctr, Kawasaki, Kanagawa, Japan

来源：

PROCEEDINGS OF THE IEEE 2002 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE | 2002年

关键词：

D O I：

10.1109/IITC.2002.1014873

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, we describe the Cu/low-k (k<3) dual-damascene process integration targeting for 90nm-node (0.28um pitch) high performance embedded DRAM devices. A stable and well-controlled dual-damascene structure was realized both by using newly developed stacked mask process (S-MAP) ([1]) and a low-damage resist ashing process. Problem, and Solutions for resist poisoning due to the stopper-SiCN layer and capping-SiO2 layer are investigated. We also demonstrated a notable via chain yield (with 2.9M vias) by applying low-k PE-CVD SiOC / SiCN dielectrics.

引用

页码：15 / 17

页数：3