Cause of erase speed degradation during two-bit per cell operation of a trapping nitride storage flash memory cell

被引：10

作者：

Tsai, WJ ^{[1
]}

Zous, NK ^{[1
]}

Chou, MH ^{[1
]}

Huang, S ^{[1
]}

Chen, HY ^{[1
]}

Yeh, YH ^{[1
]}

Liu, MY ^{[1
]}

Yeh, CC ^{[1
]}

Wang, T ^{[1
]}

Ku, J ^{[1
]}

Lu, CY ^{[1
]}

机构：

[1] Macronix Int Co Ltd, Hsinchu, Taiwan

来源：

2004 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM PROCEEDINGS | 2004年

关键词：

flash memory; two-bit per cell; trapping nitride storage; erase speed degradation; program/erase cycling; endurance; over-erasure; ONO; SONOS; NROM; MXVAND; PHINES;

D O I：

10.1109/RELPHY.2004.1315383

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Erase speed degradation in a dual-bit, trapping nitride storage flash memory cell is investigated. Our study shows that the trapped-electron area of the second-programmed bit would extend more toward the central channel region if its neighboring bit (of the same cell) has been programmed. The second bit would then be erased slower. This effect gets more obvious after program/erase cycling. In addition, the erase speed would be modulated by adjacent junction biases in a short-channel, nearly punch-through cell.

引用

页码：522 / 526

页数：5

共 13 条

[1]

ALONI E, 2000, 2000 C SOL STAT DEV, P298

[2]

Chen J, 1995, INTERNATIONAL ELECTRON DEVICES MEETING, 1995 - IEDM TECHNICAL DIGEST, P331

[3]

Cho MK, 2000, IEEE ELECTR DEVICE L, V21, P399

[4]

EITAN B, 1999, 1999 C SOL STAT DEV, P522

[5]

JANNAI M, 2003, P INT REL PHYS S, P502

[6]

*SYN, 2003, MEDICI DEV SIM

[7] Cause of data retention loss in a nitride-based localized trapping storage flash memory cell [J].

Tsai, WJ ;

Gu, SH ;

Zous, NK ;

Yeh, CC ;

Liu, CC ;

Chen, CH ;

Wang, TH ;

Pan, S ;

Lu, CY .

40TH ANNUAL PROCEEDINGS: INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM, 2002, :34-38

[8]

TSAI WJ, 2002, 2002 C SOL STAT DEV, P164

[9]

TSIA WJ, 2001, IEDM, P719

[10]

WANG T, 1998, IEEE T ELECTRON DEV, P1511

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