Investigation of interface traps in LDD pMOST's by the DCIV method

被引：27

作者：

Jie, BB ^{[1
]}

Li, MF ^{[1
]}

Lou, CL ^{[1
]}

Chim, WK ^{[1
]}

Chan, DSH ^{[1
]}

Lo, KF ^{[1
]}

机构：

[1] CHARTERED SEMICOND MFG PTE LTD,SINGAPORE 738406,SINGAPORE

来源：

IEEE ELECTRON DEVICE LETTERS | 1997年 / 18卷 / 12期

关键词：

D O I：

10.1109/55.644078

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Interface traps in submicron buried-channel LDD pMOST's, generated under different stress conditions, are investigated by the direct-current current-voltage (DCIV) technique. Two peaks C and D in the DCIV spectrum are found corresponding to interface traps generated in the channel region and in the LDD region respectively. The new DCIV results clarify certain issues of the underlying mechanisms involved on hot-carrier degradation in LDD pMOST's. Under channel hot-carrier stress conditions, the hot electron injection and electron trapping in the oxide occurs for all stressing gate voltage. How ever, the electron injection induced interface trap spatial location changes from the LDD region to the channel region when the stressing gate voltage changes from low to high.

引用

页码：583 / 585

页数：3

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