Electrical performance of Bumpless Build-Up Layer packaging

The Bumpless Build-Up Layer (BBUL) microelectronic packaging technology is characterized by the absence of a conventional substrate core and a direct extension of the outmost metallization layers of the die into the overall thin substrate. Such a coreless, thin package provides the advantages of small electrical loop inductance for power delivery and minimized discontinuities for high-speed signaling. Furthermore, it allows for reduced thermomechanical stresses on low dielectric constant (low-k) die materials, high lead count, and ready integration of multiple electronic, optical, and microelectromechanical components. BBUL is also expected to be compatible with innovative thermal solutions using frontside heat removal. After summarizing some of the non-electrical characteristics of the BBUL packaging technology we conduct transient electromagnetic (EM) simulations for the core power delivery problem. A simplistic lumped-element theory, valid for the first few nanoseconds of the transient core switching noise waveforms, is laid out initially. We then obtain distributed die voltage time-domain results for a standard six-layer flip-chip package and compare them with a model of a similar, but much thinner, three-layer BBUL package. Finally, a package capacitance reduction study indicates that a thin package as implemented by the BBUL technology and presenting a substantially reduced package loop inductance calls for the introduction of an intermediate level of decoupling in between the conventional on-die high-frequency decoupling and the on-package mid-frequency decoupling stages.