Poly-Si gate CMOSFETs with HfO2-Al2O3 laminate gate dielectric for low power applications

被引:23
作者
Lee, JH [1 ]
Kim, YS [1 ]
Jung, HS [1 ]
Lee, JH [1 ]
Lee, NI [1 ]
Kang, HK [1 ]
Ku, JH [1 ]
Kang, HS [1 ]
Kim, YK [1 ]
Cho, KH [1 ]
Sub, KP [1 ]
机构
[1] Samsung Elect Co Ltd, Adv Proc Dev Project, Syst LSI Business, Yongin 449711, Kyunggi Do, South Korea
来源
2002 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS | 2002年
关键词
D O I
10.1109/VLSIT.2002.1015399
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
For the first time, we have integratcd poly-Si gate CMOSFETs with HfO2-Al2O3 laminate gate dielectric (EOT-14.6Angstrom) grown by Atomic Layer Deposition (ALD). The gate leakage currents are 3.7muA/cm(2) (Vg=+1.0V) for nMOSFET and 0.2 muA/cm(2) (Vg=-1.0V) for pMOSFET. These extremely low leakage currents sufficiently satisfy the specification (EOT=12similar to20Angstrom, Jg=2.2mA/cm(2)) estimated by ITRS. The fixed charge is decreased using HfO2-Al2O3 laminate gate dielectric, arid consequently flatband voltage (Vfb) shift is within 0.20V compared with the Vfb of nitrided SiO2 control. In addition, the low gate induced drain leakage (GIDL) is obtained using HfO2-Al2O3 laminate gate dielectric. Ion vs. loff plots of the planar CMOS transistor with high-k is shown for the first time in this paper. The measured saturation currents at 1.2V Vdd are 430muA/mum (I-off=10nA/mum) for nMOSFET and 160muA/mum (I-off=10nA/mum) for pMOSFET. These are the highest currents compared with previous reports for the planar poly-Si gate CMOSFETs with high-k gate dielectric.
引用
收藏
页码:84 / 85
页数:2
相关论文
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Lee, NI ;
Cho, MH ;
Kim, YK ;
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Cho, KH ;
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Kim, MH ;
Fujihara, K ;
Kang, HK ;
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[3]  
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