An 18-μA standby current 1.8-V, 200-MHz microprocessor with self-substrate-biased data-retention mode

被引：41

作者：

Mizuno, H ^{[1
]}

Ishibashi, K

Shimura, T

Hattori, T

Narita, S

Shiozawa, K

Ikeda, S

Uchiyama, K

机构：

[1] Hitachi Ltd, Cent Res Lab, Tokyo 187, Japan

[2] Hitachi Ltd, Semicond & Integrated Circuits Div, Tokyo 1858601, Japan

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1999年 / 34卷 / 11期

关键词：

back bias; low-power circuits; microprocessors; substrate bias; subthreshold leakage current;

D O I：

10.1109/4.799853

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A low-standby-current 1.8-V, 200-MHz microprocessor has been fabricated with a 0.2-mu m, five-metal, dual-oxide-thickness, CMOS technology and two power-down modes (i.e., a standby mode and a data-retention mode), The microprocessor uses a switched substrate-impedance scheme to bias substrates in the standby mode while maintaining a 200-MHz operating speed. Data-retention capability during the standby mode is also maintained. This mode achieves 46.5-mu A standby current. The microprocessor also offers a battery-backup capability in a self-substrate-biased data-retention mode, This makes it possible to apply a deep substrate bias without increasing the gate-induced drain leakage current or pn junction current. The current consumption is only 17.8 mu A when operating off a 1-V supply in the data-retention mode.

引用

页码：1492 / 1500

页数：9

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