Noise margin and leakage in ultra-low leakage SRAM cell design

被引：20

作者：

Hook, TB ^{[1
]}

Breitwisch, M ^{[1
]}

Brown, J ^{[1
]}

Cottrell, P ^{[1
]}

Hoyniak, D ^{[1
]}

Lam, C ^{[1
]}

Mann, R ^{[1
]}

机构：

[1] IBM Microelect, Essex Jct, VT 05452 USA

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2002年 / 49卷 / 08期

关键词：

CMOSFETS; CMOS memory integrated circuits; random access memory (RAM);

D O I：

10.1109/TED.2002.801433

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Various aspects of ultra-low leakage static random-access memories (SRAM) cell design are considered. It is shown that the high threshold voltage relative to the power supply so improves the stability of the cell that the beta ratio of the design may be made very small for improved performance. Also, the ramifications of threshold uncertainty due to random dopant fluctuations are investigated, and it is shown that chip performance will be adversely affected by this phenomenon.

引用

页码：1499 / 1501

页数：3