A 500-MHz pipelined burst SRAM with improved SER immunity

This paper describes a 0.25-mu m, 64 K x 36 bit pipelined burst SRAM using a 6.156-mu m(2) cell. It realizes over 500-MHz operation using a lower cost double metal process, Internal 16 K x 144 organization by T-shaped bit line array reduces 20% of latency, 20% of active power, and 8.5% of die size. The low power also enables us to use lower cost thin quad flat type packages. Our solution to the soft error problem, a shallow triple well structure and four-transistor cell with stacked capacitor, improved soft error rate by 3.5 orders of magnitude compared with the conventional SRAM cell.