An FPGA-Based Fully Synchronized Design of a Bilateral Filter for Real-Time Image Denoising

In this paper, a detailed description of a synchronous field-programmable gate array implementation of a bilateral filter for image processing is given. The bilateral filter is chosen for one unique reason: It reduces noise while preserving details. The design is described on register-transfer level. The distinctive feature of our design concept consists of changing the clock domain in a manner that kernel-based processing is possible, which means the processing of the entire filter window at one pixel clock cycle. This feature of the kernel-based design is supported by the arrangement of the input data into groups so that the internal clock of the design is a multiple of the pixel clock given by a targeted system. Additionally, by the exploitation of the separability and the symmetry of one filter component, the complexity of the design is widely reduced. Combining these features, the bilateral filter is implemented as a highly parallelized pipeline structure with very economical and effective utilization of dedicated resources. Due to the modularity of the filter design, kernels of different sizes can be implemented with low effort using our design and given instructions for scaling. As the original form of the bilateral filter with no approximations or modifications is implemented, the resulting image quality depends on the chosen filter parameters only. Due to the quantization of the filter coefficients, only negligible quality loss is introduced.