A low power 1Mbit MRAM based on 1T1MTJ bit cell integrated with Copper Interconnects

被引：67

作者：

Durlam, M ^{[1
]}

Naji, P ^{[1
]}

Omair, A ^{[1
]}

DeHerrera, M ^{[1
]}

Calder, J ^{[1
]}

Slaughter, JM ^{[1
]}

Engel, B ^{[1
]}

Rizzo, N ^{[1
]}

Grynkewich, G ^{[1
]}

Butcher, B ^{[1
]}

Tracy, C ^{[1
]}

Smith, K ^{[1
]}

Kyler, K ^{[1
]}

Ren, J ^{[1
]}

Molla, J ^{[1
]}

Feil, B ^{[1
]}

Williams, R ^{[1
]}

Tehrani, S ^{[1
]}

机构：

[1] Motorola Labs, Tempe, AZ 85284 USA

来源：

2002 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS | 2002年

关键词：

D O I：

10.1109/VLSIC.2002.1015073

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A low power 1Mb Magnetoresistive Random Access Memory (MRAM) based on a I-Transistor and I-Magnetic Tunnel Junction (1T1MTJ) bit cell is demonstrated. This is the largest MRAM memory demonstration to date. In this circuit, MTJ elements are integrated with CMOS using copper interconnect technology. The copper interconnects are cladded with a high permeability layer which is used to focus magnetic flux generated by current flowing through the lines toward the MTJ devices and reduce the power needed for programming the bits. The 25mm(2) 1Mb MRAM circuit operates with address access times of less than 50ns, consuming 24mW at 3.0V and 20MHz. The circuit is fabricated in a 0.6mum CMOS process utilizing five layers of metal and two layers of poly.

引用

页码：158 / 161

页数：4