Speed and power scaling of SRAM's

Simple models for the delay, power, and area of a static random access memory (SRAM) are used to determine the optimal organizations for a SRAM and study the scaling of their speed and power with size and technology. The delay is found to increase by about one gate delay for every doubling of the RAM-size up to 1 Mb, beyond which the interconnect delay becomes an increasingly significant fraction of the total delay. With technology sealing, the nonscaling of threshold mismatches in the sense amplifiers is found to significantly impact the total delay in generations of 0.1 mu m and below.