A shallow trench isolation using LOCOS edge for preventing corner effects for 0.25/0.18 mu m CMOS technologies and beyond

Shallow trench isolation schemes using a LOGOS edge to avoid sharp corner effects are applied to 0.25 mu m and 0.18 mu m technologies. Two variations are studied. In the first case (Case A) a mini-LOGOS is grown and deglazed prior to trench etch whereas in the second case (Case B) the deglaze is omitted. Excellent narrow width effect is demonstrated. The V-T increases by less than or equal to 50mV when the transistor width is reduced from 10 mu m to 0.3 mu m. Minimum isolation space of 0.3 mu m and minimum n(+)-to-p(+) space of 0.6 mu m across a well boundary are demonstrated. Diode leakages and oxide reliability are reasonable. Transistor subthreshold characteristics show no double hump for Case A, while for Case B some devices indicate presence of double hump when a substrate back bias is applied. Despite the mini-LOGOS formation the width reductions are less than or equal to 0.05 mu m and excellent drive currents of 660 mu A/mu m (NMOS) and 290 mu A/mu m (PMOS) are achieved corresponding to I-off =1nA/mu m and V-cc = 1.8V.