An adaptive PAM-4 5 Gb/s backplane transceiver in 0.25 um CMOS

被引:11
作者
Sonntag, J [1 ]
Stonick, J [1 ]
Gorecki, J [1 ]
Beale, B [1 ]
Check, B [1 ]
Gong, XM [1 ]
Guiliano, J [1 ]
Lee, K [1 ]
Lefferts, B [1 ]
Martin, D [1 ]
Moon, UK [1 ]
Sengir, A [1 ]
Titus, S [1 ]
Wei, GY [1 ]
Weinlader, D [1 ]
Yang, Y [1 ]
机构
[1] Accelerant Networks Inc, Beaverton, OR 97006 USA
来源
PROCEEDINGS OF THE IEEE 2002 CUSTOM INTEGRATED CIRCUITS CONFERENCE | 2002年
关键词
D O I
10.1109/CICC.2002.1012844
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
This paper describes a novel backplane transceiver, which uses PAM-4 (pulse amplitude modulated four level) signalling and continuously adaptive transmit based equalization to move 5 Gcb/s (channel bits per second) across typical FR-4 back-planes for total distances of up to 50 inches through two sets of backplane connectors. The paper focuses on the implementation of the equalizer and the adaptation algorithms, and includes measured results. The 17 mm(2) device is implemented in a 0.25um CMOS process, operates on 2.5 V and 3.3 V supplies and consumes 1.2W.
引用
收藏
页码:363 / 366
页数:4
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