A 660 MB/s interface megacell portable circuit in 0.3 mu m-0.7 mu m CMOS ASIC

被引：12

作者：

Donnelly, KS

Chan, YF

Ho, JTC

Tran, CV

Patel, S

Lau, B

Kim, J

Chau, PS

Huang, C

Wei, J

Yu, L

Tarver, R

Kulkarni, R

Stark, D

Johnson, MG

机构：

[1] Rambus Incorporated, Mountain View

[2] University of California, Berkeley, CA

[3] San Jose State University, CA

[4] Rambus, Inc., Mountain View, CA

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1996年 / 31卷 / 12期

关键词：

D O I：

10.1109/4.545823

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A byte-wide I/O cell with 660 MB/s data rate uses low-jitter DLL-generated clocks, self-calibrated controlled-current drivers, and linear amplifier input receivers, The CAD techniques developed allow the design to be ported to CMOS processes ranging from 0.7 mu m to 0.3 mu m. The chip is 0.9 x 3.4 mm(2) using 0.3 mu m rules.

引用

页码：1995 / 2003

页数：9

共 7 条

[1] BOWHILL WJ, 1995, IEEE INT SOL STAT CI, P182
[2] DONNELLY K, 1996, ISSCC FEB, P290
[3] A 500-MEGABYTE/S DATA-RATE 4.5M DRAM
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OHSHIMA, S
STARK, D
NOJI, H
SAKURAI, K
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FURUYAMA, T
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CHAN, A
DILLON, J
GASBARRO, JA
GRIFFIN, MM
HOROWITZ, M
LEE, TH
LEE, V
[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1993, 28 (04) : 490 - 498
[4] A 2.5-V CMOS DELAY-LOCKED LOOP FOR AN 18-MBIT, 500-MEGABYTE/S DRAM
LEE, TH
DONNELLY, KS
HO, JTC
ZERBE, J
JOHNSON, MG
ISHIKAWA, T
[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1994, 29 (12) : 1491 - 1496
[5] SCHUTZ J, 1991, IEEE INT C SOLID STA, P90
[6] Schutz J., 1994, ISSCC, P202
[7] TAKAHASHI T, 1995, ISSCC FEB, P40

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