Development of the central trigger system for the BELLE detector at the KEK B-factory

被引：14

作者：

Ushiroda, Y

Mohapatra, A

Sakamoto, H

Sakai, Y

Nakao, M

An, Q

Wang, YF

机构：

[1] High Energy Accelerator Res Org, KEK, Div Phys, IPNS,Belle Grp, Tsukuba, Ibaraki 3050801, Japan

[2] Kyoto Univ, Dept Phys, Kyoto 6068052, Japan

[3] Utkal Univ, Dept Phys, Bhubaneswar 751004, Orissa, India

[4] Univ Sci & Technol China, Hefei 230026, Anhui, Peoples R China

来源：

NUCLEAR INSTRUMENTS & METHODS IN PHYSICS RESEARCH SECTION A-ACCELERATORS SPECTROMETERS DETECTORS AND ASSOCIATED EQUIPMENT | 1999年 / 438卷 / 2-3期

关键词：

trigger system; FPGA;

D O I：

10.1016/S0168-9002(99)00823-2

中图分类号：

TH7 [仪器、仪表];

学科分类号：

0804 ; 080401 ; 081102 ;

摘要：

In this paper, we describe the design and development of the central trigger system (CDL) for the BELLE detector at the KEK B-factory. The GDL consists of four types of single width 6U VME modules (ITD, FTD, PSNM and TMD) which are designed using the programmable logic techniques of Xilinx FPGA and CPLD. Individual and combined performance tests of these modules are done and it is confirmed that the GDL functions as expected. (C) 1999 Elsevier Science B.V. All rights reserved.

引用

页码：460 / 471

页数：12

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