Dynamic voltage scaling for systemwide energy minimization in real-time embedded systems

被引:77
作者
Jejurikar, R [1 ]
Gupta, R [1 ]
机构
[1] Univ Calif Irvine, Ctr Embedded Comp Syst, Irvine, CA 92697 USA
来源
ISLPED '04: PROCEEDINGS OF THE 2004 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN | 2004年
关键词
low power; DVS; resource standby energy; critical speed; real-time systems; EDF scheduling; procrastication;
D O I
10.1145/1013235.1013261
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Traditionally, dynamic voltage scaling (DVS) techniques have focused on minimizing the processor energy consumption as opposed to the entire system energy consumption. The slowdown resulting from DVS can increase the energy consumption of components like memory and network interfaces. Furthermore, the leakage power consumption is increasing with the scaling device technology and must also be taken into account. In this work, we consider energy efficient slowdown in a real-time task system. We present an algorithm to compute task slowdown factors based on the contribution of the processor leakage and standby energy consumption of the resources in the system. Our simulation experiments using randomly generated task sets show on an average 10% energy gains over traditional dynamic voltage scaling. We further combine slowdown with procrastination scheduling which increases the average energy savings to 15%. We show that our scheduling approach minimizes the total static and dynamic energy consumption of the systemwide resources.
引用
收藏
页码:78 / 81
页数:4
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