未找到相关数据
Novel bulk dynamic threshold voltage MOSFET (B-DTMOS) with advanced isolation (SITOS) and gate to shallow-well contact (SSS-C) processes for ultra low power dual gate CMOS
被引：27
作者：
Kotaki, H
Kakimoto, S
Nakano, M
Matsuoka, T
Adachi, K
Sugimoto, K
Fukushima, T
Sato, Y
机构：
来源：
IEDM - INTERNATIONAL ELECTRON DEVICES MEETING, TECHNICAL DIGEST 1996
|
1996年
关键词：
D O I：
10.1109/IEDM.1996.553626
中图分类号：
TM [电工技术];
TN [电子技术、通信技术];
学科分类号：
0808 ;
0809 ;
摘要：
We have developed a high speed dynamic threshold voltage MOSFET named B-DTMOS for ultra low power operation. This was realized using a bulk wafer containing an individual trench isolated shallow-well with a high concentration buried layer sandwiched between two low concentration layers surrounded by a deep well. The B-DTMOS achieved an excellent propagation delay time of 83.6psec at 0.6V operation and 103.3psec at 0.5V operation. This was realized due to ultra low body resistance of the B-DTMOS.
引用
收藏
页码：459 / 462
页数：4
相关论文