Calculation of direct tunneling gate current through ultra-thin oxide and oxide/nitride stacks in MOSFETs and H-MOSFETs

This theoretical work investigates some aspects of direct tunneling gate current in ultra-thin gate MOSFET, as influence of bias, oxide thickness, and oxide thickness fluctuations. We study two alternative device architectures to reduce this effect. They consist in either increasing the insulator thickness using a high permittivity nitride/oxide stack or burying the channel, due to a tensile strained IV-IV heterostructure. The presented calculations have been performed by coupling a semi-classical approach of direct tunneling computation with the 2D Monte Carlo device simulation. (C) 2000 Elsevier Science Ltd. All rights reserved.