Scaling the gate dielectric

被引:2
作者
Eaglesham, DJ [1 ]
机构
[1] Bell Labs, Lucent Technol, Murray Hill, NJ 07974 USA
来源
MICROELECTRONIC DEVICE TECHNOLOGY III | 1999年 / 3881卷
关键词
D O I
10.1117/12.360539
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
The gate dielectric is arguably the biggest challenge facing the physical scaling of the MOSFET. The alternatives to continued scaling of SiO2 include radical departures from standard process flows and very challenging new materials issues. In the short term, the industry continues to pursue improvements to the reliability and tunneling performance of silicon-dioxide. New data on reliability suggests that SiO2 as thin as 1.6nm may achieve acceptable reliability in the field. Beyond SiO2, there is no material which has yet demonstrated comparable reliability or interface-state-density. The most promising approach involves using sandwiched high-k materials, with thin SiO2 at both interfaces. Either Ta2O5 or TiO2 may be suitable in structures of this type.
引用
收藏
页码:2 / 7
页数:6
相关论文
共 3 条
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Degraeve R., 1999, 1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325), P59, DOI 10.1109/VLSIT.1999.799339
[2]   Reliability projection for ultra-thin oxides at low voltage [J].
Stathis, JH ;
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INTERNATIONAL ELECTRON DEVICES MEETING 1998 - TECHNICAL DIGEST, 1998, :167-170
[3]  
WEIR BE, 1999, IN PRESS IEDM