Optimal supply and threshold scaling for subthreshold CMOS circuits

被引:119
作者
Wang, A [1 ]
Chandrakasan, AP [1 ]
Kosonocky, SV [1 ]
机构
[1] MIT, Dept EECS, Cambridge, MA 02139 USA
来源
ISVLSI 2000: IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI - NEW PARADIGMS FOR VLSI SYSTEMS DESIGN | 2002年
关键词
D O I
10.1109/ISVLSI.2002.1016866
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
With technology scaling, power supply and threshold voltage continue to decrease to satisfy high performance and low power requirements. In the past, subthreshold CMOS circuits have been inadequate for high performance applications, but have been used in applications that require ultra low power dissipation. Many applications including medical and wireless applications, require ultra low power dissipation with low-to-moderate performance (10kHz-100MHz). In this work, using BSIM3 models, the performance and energy dissipation of 0.18-mum CMOS circuits for the range of V-dd=0.1-0.6V and V-th=0-0.6V are analyzed to show that subthreshold CMOS circuits can be used in low performance applications. A simple characterization circuit is introduced which can be used to evaluate the performance and energy dissipation for a given process under varying activity. These results are useful in circuit design by giving insight into optimal voltage supply and threshold voltage operation for a given application specification. Characterization results show that operation at the optimal V-dd-V-th voltage levels can lead to an order of magnitude energy savings. Also additional analysis into V-th and temperature variations is included.
引用
收藏
页码:7 / 11
页数:5
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