Three-stage large capacitive load amplifier with damping-factor-control frequency compensation

A novel damping-factor-control frequency compensation (DFCFC) technique is presented in this paper with detailed theoretical analysis, This compensation technique improves frequency response, transient response, and power supply rejection for amplifiers, especially when driving large capacitive loads. Moreover, the required compensation capacitors are small and can be easily integrated in commercial CMOS process. Amplifiers using DFCFC and nested Miller compensation (NMC) driving two capacitive loads, 100 and 1000 pF, were fabricated using a 0.8 mu m CMOS process with V-m = 0.72 V and V-tp = -0.75 V, For the DFCFC amplifier driving a 1000-pF load, a 1-MHz gain-bandwidth product, 51 degrees phase margin, 0.33-V/mu s slew rate, 3.54-mu s settling time, and 426-mu W power consumption are obtained with integrated compensation capacitors. Compared to the NMC amplifier, the frequency and transient responses of the DFCFC amplifier are improved by one order of magnitude with insignificant increase on the power consumption.