Analysis and design of a robust average current mode control loop for parallel buck DC-DC converters to reduce line and load disturbance

被引:21
作者
Garcerá, G
Figueres, E
Pascual, M
Benavent, JM
机构
[1] Univ Politecn Valencia, Dept Ingn Elect, Valencia 46022, Spain
[2] Univ Politecn Valencia, Escuela Politecn Super Alcoy, Alcoy 03801, Alicante, Spain
来源
IEE PROCEEDINGS-ELECTRIC POWER APPLICATIONS | 2004年 / 151卷 / 04期
关键词
D O I
10.1049/ip-epa:20040319
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 [电气工程]; 0809 [电子科学与技术];
摘要
A robust control scheme for multi-module parallel buck DC-DC converters with average current mode control (ACC) is presented. The proposed loop adds an inner loop to the conventional current and voltage ACC loops, reducing the sensitivity of the outer voltage loop to the changing power stage parameters: number of modules, input voltage, load and component tolerances. The loop improves significantly the disturbance rejection of the converter, i.e. the closed loop output impedance and audiosusceptibility, while preserving the stability and the loop gain crossover frequency to a significant extent. The performance of the proposed scheme is demonstrated by both small-signal and large signal experimental results.
引用
收藏
页码:414 / 424
页数:11
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