Erase/write cycle tests of n-MOSFET's with Si-implanted gate-SiO2

被引：18

作者：

Ohzone, T ^{[1
]}

Matsuda, T ^{[1
]}

Hori, T ^{[1
]}

机构：

[1] MATSUSHITA ELECT IND CO LTD, SEMICOND RES CTR, OSAKA 570, JAPAN

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 1996年 / 43卷 / 09期

关键词：

D O I：

10.1109/16.535321

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

For discussing an applicability of a MOSFET with Si-implanted gate-SiO2 of 50 nm thickness to a non volatile random access memory (NVRAM) operating more than 3.3 x 10(15) erase/write (E/W) cycles, E/W-cycle tests were performed up tea 10(11) cycles by measuring a hysteresis curve observed in a source follower MOSFET in which a sine-wave voltage of 100 kHz was supplied tea the gate, Degradations in a threshold-voltage window of 15 V and a gain factor were scarcely observed in a MOSFET with Si-implantation at 50 keV/1 x 10(16) cm(-2) at a gate voltage of +/-40 V, Those degradations observed in a MOSFET with 25 keV/3 x 10(16) cm(-2) were improved by lowering the gate voltage from +/-40 V to +/-30 V in sacrificing the smaller threshold-voltage window from 20 to 8.5 V.

引用

页码：1374 / 1381

页数：8