A monolithic optoelectronic receiver in standard 0.7-mu m CMOS operating at 180 MHz and 176-fJ light input energy

A novel monolithic optoelectronic receiver/converter system is presented in standard 0.7-mu m N-well CMOS technology. Differential light input incident on enlarged drains of two MOS transistors of a sense amplifier induces latching in either the digital HIGH state or the digital LOW state. The enlarged drains serve as photodiodes, circumventing hybridization techniques like flip-chip and/or solderbumping necessary when using III-V photodiodes. The first receivers of this type have photodetector areas of 15 x 15 mu m(2) and demonstrate bitrates of 180 Mb/s with a differential light input of 176 fJ. The electrical power dissipation is of the order of the dissipation of one CMOS logic gate. The very small total receiver area makes the receiver further perfectly suited for use in massive parallel optical interconnects between VLSI chips.