Mechanical reliability in electronic packaging

The dramatic increase in the number of devices and functionality of the latest ultra large scale integration designs have resulted in increasing chip size. Concurrently, to achieve higher circuit board component densities, package dimensions have been shrinking. These two competing trends are leading to ever more rigorous requirements on the mechanical characteristics of the packaging technology. The dominant issue in component level reliability is delamination and cracks initiated at the interface between dissimilar materials. In board level reliability, solder joint reliability is a primary issue. This paper describes the methodology of prediction and the explanation for interfacial delamination, cracks at the top of the interfaces and the edge of corner, and also solder joint reliability, This paper furthermore presents the role of the chip backside contamination affecting interfacial delamination, the surface characterizations and an explanation of the interface chemistry, and the strength of solders with a variety of plating materials for Sn-Ag-based lead free solders. (C) 2002 Elsevier Science Ltd. All rights reserved.