A 4GHz 130nm address generation unit with 32-bit sparse-tree adder core

被引：27

作者：

Mathew, S ^{[1
]}

Anders, M ^{[1
]}

Krishnamurthy, R ^{[1
]}

Borkar, S ^{[1
]}

机构：

[1] Intel Corp, Intel Labs, Circuits Res, Hillsboro, OR 97124 USA

来源：

2002 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS | 2002年

关键词：

D O I：

10.1109/VLSIC.2002.1015063

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper describes a 32-bit Address Generation Unit (AGU) designed for 4GHz operation in 1.2V, 130nm technology. The AGU utilizes a 152ps dual-V-t sparse-tree adder core to achieve 20% delay reduction, 80% lower interconnect density and a low (1%) active energy leakage component. The semidynamic implementation enables an average energy profile similar to static CMOS, with good sub-130nm scaling trend.

引用

页码：126 / 127

页数：2