A high-frequency custom CMOS S/390 microprocessor

The S/390(R) Parallel Enterprise Server Generation 4 processor is an implementation of the IBM ESA/390(TM) architecture on a single custom CMOS chip. It was designed on a blank slate after consideration of remapping either a prior CMOS design or a prior bipolar design. It uses a straightforward pipeline both to achieve a fast cycle time and to speed the design cycle. The complex instructions are implemented using highly privileged subroutines called millicode. To achieve high data integrity while maintaining a high clock frequency, the chip contains duplicate I-and E-units which perform the same operations each cycle and have their results compared.