PipeRench: A reconfigurable architecture and compiler

被引：207

作者：

Goldstein, SC ^{[1
]}

Schmit, H

Budiu, M

Cadambi, S

Moe, M

Taylor, RR

机构：

[1] Carnegie Mellon Univ, Sch Comp Sci, Pittsburgh, PA 15213 USA

[2] Carnegie Mellon Univ, Dept Comp Sci, Pittsburgh, PA 15213 USA

[3] Carnegie Mellon Univ, Dept Elect & Comp Engn, Pittsburgh, PA 15213 USA

来源：

COMPUTER | 2000年 / 33卷 / 04期

关键词：

D O I：

10.1109/2.839324

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

With the proliferation of highly specialized embedded computer systems has come a diversification of workloads for computing devices. General-purpose processors are struggling to efficiently meet these applications' disparate needs, and custom hardware is rarely feasible. According to the authors, reconfigurable computing, which combines the flexibility of general-purpose processors with the efficiency of custom hardware, can provide the alternative. PipeRench and its associated compiler comprise the authors' new architecture for reconfigurable computing. Combined with a traditional digital signal processor, microcontroller, or general-purpose processor, PipeRench can support a system's various computing needs without requiring custom hardware. The authors describe the PipeRench architecture and how it solves some of the preexisting problems with FPGA architectures, such as logic granularity, configuration time, forward compatibility, hard constraints, and compilation time.

引用

页码：70 / +

页数：9