Defect and error tolerance in the presence of massive numbers of defects

被引：160

作者：

Breuer, MA

Gupta, SK

机构：

[1] Univ So Calif, Dept Elect Engn, Los Angeles, CA 90089 USA

[2] Univ So Calif, Dept Elect Engn Syst, Los Angeles, CA 90089 USA

[3] Intel Corp, Design Technol Grp, Santa Clara, CA 95051 USA

来源：

IEEE DESIGN & TEST OF COMPUTERS | 2004年 / 21卷 / 03期

关键词：

D O I：

10.1109/MDT.2004.8

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 [计算机科学与技术];

摘要：

Several design and test issues that help compensate for increase defect rates of semiconductor device are discussed in this article. A new application-oriented paradigm-error tolerance-for dealing with process variations, defects and noise. This paradigm incorporates design and test techniques to support a measure of yield that only includes die (after configuration, if applicable) with error-face I/O behavior but also die that produce only errors deemed acceptable for the system in which they will be embedded.

引用

页码：216 / 227

页数：12