Development of ultra-low impedance through-wafer micro-vias

被引:7
作者
Finkbeiner, FM
Adams, C
Apodaca, E
Chervenak, JA
Fischer, J
Doan, N
Li, MJ
Stahle, CK
Brekosky, RP
Bandler, SR
Figueroa-Feliciano, E
Lindeman, MA
Kelley, RL
Saab, T
Talley, DJ
机构
[1] NASA, GSFC, SSAI, Lanham, MD USA
[2] NASA, Goddard Space Flight Ctr, Greenbelt, MD 20771 USA
[3] NASA, GSFC, QSS, Lanham, MD USA
[4] AlumiPlate Inc, Minneapolis, MN 55433 USA
[5] Swales Aerosp, Beltsville, MD USA
[6] Univ Maryland, Dept Astron, College Pk, MD 20742 USA
关键词
through-wafer micro-via; high-aspect ratio etching; PPR electro-deposition; cryogenic temperatures;
D O I
10.1016/j.nima.2003.11.373
中图分类号
TH7 [仪器、仪表];
学科分类号
0804 ; 080401 ; 081102 ;
摘要
Concurrent with our microcalorimeter array fabrication for Constellation-X technology development, we are developing ultra-low impedance Through-Wafer Micro-Vias (TWMV) as electrical interconnects for superconducting circuits. The TWMV will enable the electrical contacts of each detector to be routed to contacts on the backside of the array. There, they can be bump-bonded to a wiring fan-out board which interfaces with the front-end Superconducting Quantum Interference Device readout. We are concentrating our developmental efforts on ultra-low impedance copper and superconducting aluminum TWMV in 300-400 micron thick silicon wafers. For both schemes, a periodic pulse-reverse electroplating process is used to fill or coat micron-scale through-wafer holes of aspect ratios up to 20. Here we discuss the design, fabrication process, and recent electro-mechanical test results of Al and Cu TWMV at room and cryogenic temperatures. (C) 2003 Elsevier B.V. All rights reserved.
引用
收藏
页码:463 / 465
页数:3
相关论文
共 3 条
[1]   Mechanical reliability of silicon wafers with through-wafer vias for wafer-level packaging [J].
Polyakov, A ;
Bartek, M ;
Burghartz, JN .
MICROELECTRONICS RELIABILITY, 2002, 42 (9-11) :1783-1788
[2]   Pulse reverse copper electrodeposition in high aspect ratio trenches and vias [J].
West, AC ;
Cheng, CC ;
Baker, BC .
JOURNAL OF THE ELECTROCHEMICAL SOCIETY, 1998, 145 (09) :3070-3074
[3]   A high aspect-ratio silicon substrate-via technology and applications: Through-wafer interconnects for power and ground and faraday cages for SOC isolation [J].
Wu, JH ;
del Alamo, JA ;
Jenkins, KA .
INTERNATIONAL ELECTRON DEVICES MEETING 2000, TECHNICAL DIGEST, 2000, :477-480