The impact of iron, copper, and calcium contamination of silicon surfaces on the yield of a MOS dram test process

被引：30

作者：

Burte, EP

Aderhold, W

机构：

[1] Fraunhofer-Inst. Integrierte S., Bauelementetechnologie, D-91058 Erlangen

来源：

SOLID-STATE ELECTRONICS | 1997年 / 41卷 / 07期

关键词：

D O I：

10.1016/S0038-1101(97)00016-6

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The impact of the silicon surface contaminants iron, copper and calcium on gate oxide integrity was investigated quantitatively by evaluating MOS test capacitors built on intentionally contaminated wafers. All three elements influenced dielectric breakdown field strength and charge to breakdown values if the surface contamination level was raised beyond 10(9) to 10(10) atoms/cm(2). The distribution of these elements in the silicon oxide could be related to electrical yield measurements. (C) 1997 Elsevier Science Ltd.

引用

页码：1021 / 1025

页数：5