Increasing processor performance by implementing deeper pipelines

被引:92
作者
Sprangle, E [1 ]
Carmean, D [1 ]
机构
[1] Intel Corp, Architecture Grp, Santa Clara, CA 95051 USA
来源
29TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE, PROCEEDINGS | 2002年
关键词
D O I
10.1109/ISCA.2002.1003559
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
One architectural method for increasing processor performance involves increasing the frequency by implementing deeper pipelines. This paper will explore the relationship between performance and pipeline depth using a Pentium(R) 4 processor like architecture as a baseline and will show that deeper pipelines can continue to increase performance. This paper will show that the branch misprediction latency is the single largest contributor to performance degradation as pipelines are stretched, and therefore branch prediction and fast branch recovery will continue to increase in importance. We will also show that higher performance cores, implemented with longer pipelines for example, will put more pressure on the memory system, and therefore require larger on-chip caches. Finally, we will show that in the same process technology, designing deeper pipelines can increase the processor frequency by 100%, which, when combined with larger on-chip caches can yield performance improvements of 35% to 90% over a Pentium(R) 4 like processor.
引用
收藏
页码:25 / 34
页数:10
相关论文
共 10 条
[1]  
COLWELL R, 1995, ISSCC FEB, P176
[2]  
FRIENDLY DH, 1997, P 39 ANN ACM IEEE IN
[3]  
HARRIS D, SKEW TOLERANT CIRCUI
[4]  
HOROWITZ M, 1999, P SEM RES CORP WORKS
[5]   The alpha 21264 microprocessor [J].
Kessler, RE .
IEEE MICRO, 1999, 19 (02) :24-36
[6]  
Kumar R., private communication
[7]  
KURD N, 2001, IEEE INT SOL STAT CI, P404
[8]  
SAGER D, COMMUNICATION
[9]  
SAGER D, 2001, ISSCC, P324
[10]  
SEZNEC A, 1996, P 7 INT C ARCH SUPP, P116