Investigation of multi-level-cell and SET operations on super-lattice phase change memories

被引:15
作者
Egami, Toru [1 ]
Johguchi, Koh [1 ]
Yamazaki, Senju [1 ]
Takeuchi, Ken [1 ]
机构
[1] Chuo Univ, Bunkyo Ku, Tokyo 1128551, Japan
基金
日本学术振兴会;
关键词
D O I
10.7567/JJAP.53.04ED02
中图分类号
O59 [应用物理学];
学科分类号
摘要
This paper gives the optimum SET pulse with the investigation on SET current delay and the multi-level-cell (MLC) operation for super-lattice phase change memories (SL-PCMs). From the investigation, the voltage, or the electric field triggers RESET/SET transition of SL-PCM. The induced energy is also essential for changing the resistance state. In this paper, the MLC operation is also verified with RESET pulse, 1-step SET pulse and 2-step SET pulse. The measurement results indicate the 2-step SET pulse is the best for the MLC function, which realizes the precise resistance controlling. Additionally, the retention-time is measured to evaluate the reliability of MLC SL-PCM. The features of SL-PCM are not only small RESET/SET current, but also MLC operation and the SL-PCM technology provides a potential for next generation non-volatile memories. (C) 2014 The Japan Society of Applied Physics
引用
收藏
页数:8
相关论文
共 31 条
[1]  
Bez R., 2009, IEDM Tech. Dig, P89
[2]  
Braga S., 2011, IEEE INT MEMORY WORK
[3]  
Burcin L, 2005, AEROSP CONF PROC, P2485
[4]  
Cabrini A., 2008, 2008 15th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2008), P186, DOI 10.1109/ICECS.2008.4674822
[5]  
CHEN YC, 2006, IEDM TECH DIG
[6]  
Egami T., 2013, INT CONF ON SOLID ST
[7]  
Gill M., 2002, DIG TECH PAP IEEE IN, P158
[8]   Program window of doped Sb2Te phase change line cells [J].
Jedema, F. J. ;
in 't Zandt, M. A. A. .
APPLIED PHYSICS LETTERS, 2007, 91 (20)
[9]  
Johguchi K, 2013, INT RELIAB PHY SYM
[10]   x10 Fast write, 80% energy saving temperature controlling set method for multi-level cell phase change memories to solve the scaling blockade [J].
Johguchi, Koh ;
Shintani, Toshimichi ;
Morikawa, Takahiro ;
Yoshioka, Kazuaki ;
Takeuchi, Ken .
SOLID-STATE ELECTRONICS, 2013, 81 :78-85