Superior nMOSFET scalability using fluorineine co-implantation and spike annealing

被引：1

作者：

Kubicek, S. ^{[1
]}

Hoffmann, T. ^{[1
]}

Augendre, E. ^{[1
]}

Pawlak, B. ^{[2
]}

Chiarella, T. ^{[1
]}

Kerner, C. ^{[1
]}

Severi, S. ^{[1
]}

Falepin, A. ^{[1
]}

De Keersgieter, A. ^{[1
]}

Noda, T. ^{[1
,3
]}

Jurczak, M. ^{[1
]}

Absil, P. ^{[1
]}

Biesemans, S. ^{[1
]}

机构：

[1] IMEC, Louvain, Belgium

[2] Philips Res, Leuven, Belgium

[3] IMEC, Matsushita Elect Assignce, Leuven, Belgium

来源：

ASDAM '06: SIXTH INTERNATIONAL CONFERENCE ON ADVANCED SEMICONDUCTOR DEVICES AND MICROSYSTEMS, CONFERENCE PROCEEDINGS | 2006年

关键词：

D O I：

10.1109/ASDAM.2006.331164

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We report the simultaneous improvement of both on- and off-properties for nMOSFETs by means of Fluorineine co-implantation at extension level, using conventional spike annealing. For the first time, spike-annealed NFETs with Fluorineine co-implanted source/drain extensions (SDE) are shown to outperform conventional As-implanted and C co-implanted devices in the deca-nanometric range. Parameters such as on-current, drain-induced barrier lowering (DIBL), external resistance (R-EXT) vs. effective channel length (Leff) trade-off are examined.

引用

页码：101 / 104

页数：4