Early analysis tools for system-on-a-chip design

被引:19
作者
Darringer, JA
Bergamaschi, RA
Bhattacharya, S
Brand, D
Herkersdorf, A
Morrell, JK
Nair, II
Sagmeister, P
Shin, Y
机构
[1] IBM Corp, Div Res, Thomas J Watson Res Ctr, Yorktown Hts, NY 10598 USA
[2] IBM Corp, Zurich Res Lab, Div Res, CH-8803 Ruschlikon, Switzerland
[3] IBM Corp, Microelect Div, E Fishkill Facil, Hopewell Jct, NY 12533 USA
关键词
D O I
10.1147/rd.466.0691
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
The paper describes the need for early analysis tools to enable developers of today's system-on-a-chip (SoC) designs to take advantage of pre-designed components, such as those found in the IBM Blue Logic(R) Library, and rapidly explore high-level design alternatives to meet their system requirements. We report on a new approach for developing high-level performance models for these SoC designs and outline how this performance analysis capability can be integrated into an overall environment for efficient SoC design.
引用
收藏
页码:691 / 707
页数:17
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