A 70 nm gate length CMOS technology with 1.0 V operation

被引：27

作者：

Ono, A ^{[1
]}

Fukasaku, K ^{[1
]}

Matsuda, T ^{[1
]}

Fukai, T ^{[1
]}

Ikezawa, N ^{[1
]}

Imai, K ^{[1
]}

Horiuchi, T ^{[1
]}

机构：

[1] NEC Corp Ltd, ULSI Device Dev Labs, Sagamihara, Kanagawa 2291198, Japan

来源：

2000 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS | 2000年

关键词：

D O I：

10.1109/VLSIT.2000.852750

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A 70-nm gate length CMOS technology for 1.0 V operation has been developed. This technology realizes high performance CMOS roadmap trend and utilizes sub-1 keV ion implantation for source/drain extension formations, quick-cooling RTA process, and ultra-thin gate dielectrics of 1.3 nm. The thickness of the gate dielectrics has been optimized in terms of both the I-ON- I-OFF trade-off and gate delay metrics. Obtained(D)(SAT) for nMOS and pMOS are 723 mu A/mu m (I-OFF = 16 nA/mu m) and 290 mu A/mu m (I-OFF = 20 nA/mu m), respectively.

引用

页码：14 / 15

页数：2

共 5 条

[1]

[Anonymous], 1999, INT TECHNOLOGY ROADM

[2]

Ghani T., 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318), P415, DOI 10.1109/IEDM.1999.824182

[3]

Mehrotra M., 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318), P419, DOI 10.1109/IEDM.1999.824183

[4]

Song S., 1999, IEDM, P427

[5] Progress toward 10nm CMOS devices [J].

Timp, G ;

Bourdelle, KK ;

Bower, JE ;

Baumann, FH ;

Boone, T ;

Cirelli, R ;

Evans-Lutterodt, K ;

Garno, J ;

Ghetti, A ;

Gossmann, H ;

Green, M ;

Jacobson, D ;

Kim, Y ;

Kleiman, R ;

Klemens, F ;

Kornblit, A ;

Lochstampfor, C ;

Mansfield, W ;

Moccio, S ;

Muller, DA ;

Ocola, LE ;

O'Malley, ML ;

Rosamilia, J ;

Sapjeta, J ;

Silverman, P ;

Sorsch, T ;

Tennant, DM ;

Timp, W ;

Weir, BE .

INTERNATIONAL ELECTRON DEVICES MEETING 1998 - TECHNICAL DIGEST, 1998, :615-618

← 1 →