A 1.8-mW CMOS ΣΔ modulator with integrated mixer for A/D conversion of IF signals

被引：55

作者：

Breems, LJ ^{[1
]}

van der Zwan, EJ

Huijsing, JH

机构：

[1] Delft Univ Technol, NL-2628 CD Delft, Netherlands

[2] Philips Res Labs, NL-5656 AA Eindhoven, Netherlands

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2000年 / 35卷 / 04期

关键词：

analog-digital conversion; CMOS analog integrated circuits; continuous-time modulation; harmonic distortion; IF mixer; radio receivers; sigma-delta modulation;

D O I：

10.1109/4.839907

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, the design of a continuous-time baseband sigma-delta (Sigma Delta) modulator with an integrated mixer for intermediate-frequency (IF) analog-to-digital conversion is presented. This highly linear IF Sigma Delta modulator digitizes a GSM channel at intermediate frequencies up to 50 MHz. The sampling rate is not related to the input IF and is 13.0 MHz in this design. power consumption is 1.8 mW from a 2.5-V supply. Measured dynamic range is 82 dB, and third-order intermodulation distortion is -84 dB for two -6-dBV IF input tones. Two modulators in quadrature configuration provide 200-kHz GSM bandwidth. Active area of a single IF Sigma Delta modulator is 0.2 mm(2) in 0.35-mu m CMOS.

引用

页码：468 / 475

页数：8

共 16 条

[1]

ADAMS RW, 1986, J AUDIO ENG SOC, V34, P153

[2]

Breems L. J., 1999, ESSCIRC'99. Proceedings of the 25th European Solid-State Circuits Conference, P318

[3]

BREEMS LJ, 1999, IEEE INT SOL STAT CI, P52

[4] A single-chip 900 MHz CMOS receiver front-end with a high performance low-IF topology [J].