Verification of overlap and fringing capacitance models for MOSFETs

被引：13

作者：

Wakita, N ^{[1
]}

Shigyo, N ^{[1
]}

机构：

[1] Toshiba Corp Semicond Co, Syst LSI Design Div, Sakae Ku, Yokohama, Kanagawa 2478585, Japan

来源：

SOLID-STATE ELECTRONICS | 2000年 / 44卷 / 06期

关键词：

Capacitance - Computer simulation - Semiconductor device models - VLSI circuits;

D O I：

10.1016/S0038-1101(99)00331-7

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Parasitic capacitance and resistance limit the VLSI device performance. Hence, a circuit model is needed to treat these effects correctly. This article focuses on the circuit models for the overlap capacitance (C-gd.overlap) and the fringing capacitance (C-gd.fringe) of MOSFETs. Comparisons between the models and the device simulations are carried out for verification of the models. Also, a limitation of C-gd.fringe model for a future device miniaturization is found based on SIA Road Map. We propose a modified C-gd.fringe model. The effectiveness of the modified model is demonstrated using two circuits. (C) 2000 Elsevier Science Ltd. All rights reserved.

引用

页码：1105 / 1109

页数：5