Numerical analysis of slow current transients and power compression in GaAsFETs

被引：26

作者：

Kazami, Y ^{[1
]}

Kasai, D ^{[1
]}

Horio, K ^{[1
]}

机构：

[1] Shibaura Inst Technol, Fac Syst Engn, Saitama, Saitama 3378570, Japan

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2004年 / 51卷 / 11期

关键词：

drain-lag; GaAs MESFET; gate-lag; impact ionization; power compression; substrate trap; surface state;

D O I：

10.1109/TED.2004.837383

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Two-dimensional transient simulation of GaAs MESFETs is performed when the gate voltage and the drain voltage are both changed abruptly. Quasi-pulsed current-voltage (I-V) curves are derived from the transient characteristics. It is discussed how the slow current transients (lag phenomena) and the pulsed I-V curves are affected by the existence of substrate traps and surface states. It is shown that the so-called power compression could occur both due to substrate traps and due to surface states; Effects of impact ionization of carriers on these phenomena are also discussed. It is shown that the lag phenomena and the power-compression are weakened when impact ionization of carriers becomes important, because generated holes may help the traps to change their ionized densities quickly.

引用

页码：1760 / 1764

页数：5

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