Scalability of partially depleted SOI technology for sub-0.25μm logic applications

被引：20

作者：

Chau, R ^{[1
]}

Arghavani, R ^{[1
]}

Alavi, M ^{[1
]}

Douglas, D ^{[1
]}

Greason, J ^{[1
]}

Green, R ^{[1
]}

Tyagi, S ^{[1
]}

Xu, J ^{[1
]}

Packan, P ^{[1
]}

Yu, S ^{[1
]}

Liang, CL ^{[1
]}

机构：

[1] Intel Corp, Portland Technol Dev, Hillsboro, OR 97124 USA

来源：

INTERNATIONAL ELECTRON DEVICES MEETING - 1997, TECHNICAL DIGEST | 1997年

关键词：

D O I：

10.1109/IEDM.1997.650454

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The scalability of partially depleted (PD) SOI with a floating body has been evaluated to below the sub-0.25 mu m regime using transistors, ring oscillators and 4 Mb SRAMs as test vehicles. In this paper the speed and power performance of PD-SOI are compared to those of bulk for 1.8V/sub-0.25 mu m logic applications. In addition, the 4Mb SOI SRAM yield issues are revealed. Using the same transistor off-state leakage current limit criterion for both bulk and SOI, we conclude that PD-SOI with a floating body will provide no speed and insignificant power advantage over bulk for sub-0.25 mu m logic applications.

引用

页码：591 / 594

页数：4