Low temperature metal-based cell integration technology for gigabit and embedded DRAMs

被引：13

作者：

Yoshida, M ^{[1
]}

Kumauchi, T ^{[1
]}

Kawakita, K ^{[1
]}

Ohashi, N ^{[1
]}

Enomoto, H ^{[1
]}

Umezawa, T ^{[1
]}

Yamamoto, N ^{[1
]}

Asano, I ^{[1
]}

Tadaki, Y ^{[1
]}

机构：

[1] Hitachi Ltd, Device Dev Ctr, Tokyo, Japan

来源：

INTERNATIONAL ELECTRON DEVICES MEETING - 1997, TECHNICAL DIGEST | 1997年

关键词：

D O I：

10.1109/IEDM.1997.649451

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

An advanced memory cell structure with poly/metal word lines and metal bit lines is proposed. The thermal processes are carefully designed for the metal-based cell to be consistent with narrow gap filling, wet cleaning, planarity, and the contact process. The extremely low temperature process also helps suppress the short channel effect of the MOS transistors. The fully-self-aligned contact and via-hole technology provides the minimum memory cell area. This technology is promising for future gigabit DRAMs and embedded DRAMs.

引用

页码：41 / 44

页数：4