Full copper wiring in a sub-0.25 μm CMOS ULSI technology

被引：449

作者：

Edelstein, D ^{[1
]}

Heidenreich, J ^{[1
]}

Goldblatt, R ^{[1
]}

Cote, W ^{[1
]}

Uzoh, C ^{[1
]}

Lustig, N ^{[1
]}

Roper, P ^{[1
]}

McDevitt, T ^{[1
]}

Motsiff, W ^{[1
]}

Simon, A ^{[1
]}

Dukovic, J ^{[1
]}

Wachnik, R ^{[1
]}

Rathore, H ^{[1
]}

Schulz, R ^{[1
]}

Su, L ^{[1
]}

Luce, S ^{[1
]}

Slattery, J ^{[1
]}

机构：

[1] IBM Corp, Semicond Res & Dev Ctr, Hopewell Junction, NY 12533 USA

来源：

INTERNATIONAL ELECTRON DEVICES MEETING - 1997, TECHNICAL DIGEST | 1997年

关键词：

D O I：

10.1109/IEDM.1997.650496

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We present the first fully integrated ULSI CMOS/copper interconnect technology. Up to 6 Cu wiring levels are built at minimum metal-contacted pitch of 0.63 mu m, with W local-interconnect and contact levels and a polycontacted pitch of 0.81 mu m, on a fully-scaled sub 0.25 mu m, 1.8V CMOS technology. The Cu wiring has advantages of significantly lower resistance, higher allowed current density, and increased scalability, relative to comparable Ti/Al(Cu) wiring(1). These benefits in turn have enabled the scaling of pitch and thickness, fi om reduced-capacitance, high-density lower levels to low-RC global wiring levels, consistent with high-performance and high-density needs. The integrated Cu hardware was evaluated according to a comprehensive set of yield, reliability, and stress tests. This included fully functional, high-density 288K SRAM chips which were packaged into product modules and successfully tested for reliability. Overall, we find the results for full Cu wiring meet or exceed the standards set by our Al(Cu)/W-stud technology.

引用

页码：773 / 776

页数：4