Implications of area-array I/O for row-based placement methodology

被引：28

作者：

Caldwell, A ^{[1
]}

Kahng, AB ^{[1
]}

Mantik, S ^{[1
]}

Markov, IL ^{[1
]}

机构：

[1] Univ Calif Los Angeles, Dept Comp Sci, Los Angeles, CA 90095 USA

来源：

IEEE SYMPOSIUM ON IC/PACKAGE DESIGN INTEGRATION - PROCEEDINGS | 1998年

关键词：

D O I：

10.1109/IPDI.1998.663636

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

We empirically study the implications of area.-array I/O for placement methodology. Our work develops a three-axis testbed that examines (1) I/O pad regime (area-array vs. peripheral pad locations), (2) I/O and core placement methodology (variants of alternating vs. simultaneous I/O and core placement approaches), and (3) placement engine (hierarchical quadratic for both core and I/O cells vs. pure min-cut for core cells and assignment for I/O). Experimental data show that the area-array I/O regime is somewhat "more forgiving" of bad placement methodologies than the peripheral I/O regime. On the other band, the wrong methodology can still entail substantial losses in solution quality and efficiency.

引用

页码：93 / 98

页数：6