Intrinsic leakage in low power deep submicron CMOS ICs

被引：102

作者：

Keshavarzi, A ^{[1
]}

Roy, K ^{[1
]}

Hawkins, CF ^{[1
]}

机构：

[1] Intel Corp, Rio Rancho, NM 87124 USA

来源：

ITC - INTERNATIONAL TEST CONFERENCE 1997, PROCEEDINGS: INTEGRATING MILITARY AND COMMERCIAL COMMUNICATIONS FOR THE NEXT CENTURY | 1997年

关键词：

D O I：

10.1109/TEST.1997.639607

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The large leakage currents in deep transistors threaten future products and quality manufacturing techniques. These include the ability to manufacture low power and battery operated products, and the ability to perform I-DDQ sensitive measurements with the significant ensuing benefits to test, reliability, and failure analysis. This paper reports transistor intrinsic leakage reduction as functions of bias point, temperature, source-well backbiasing, and lowered power supply (V-DD). These device properties are applied to a test application that combines I-DDQ and F-MAX to establish a 2-parameter limit for distinguishing intrinsic and extrinsic (defect) leakages in microprocessors with high background I-DDQ leakage.

引用

页码：146 / 155

页数：10