A 0.10μm gate length CMOS technology with 30Å gate dielectric for 1.0V-1.5V applications

被引：25

作者：

Rodder, M ^{[1
]}

Hanratty, M ^{[1
]}

Rogers, D ^{[1
]}

Laaksonen, T ^{[1
]}

Hu, JC ^{[1
]}

Murtaza, S ^{[1
]}

Chao, CP ^{[1
]}

Hattangady, S ^{[1
]}

Aur, S ^{[1
]}

Amerasekera, A ^{[1
]}

Chen, IC ^{[1
]}

机构：

[1] Texas Instruments Inc, Ctr Semicond Proc & Design, Dallas, TX 75265 USA

来源：

INTERNATIONAL ELECTRON DEVICES MEETING - 1997, TECHNICAL DIGEST | 1997年

关键词：

D O I：

10.1109/IEDM.1997.650349

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

High performance 0.1 mu m (physical) gate length CMOS with 30 Angstrom gate dielectric (C-V: gate accumulated at V-gb=-3V) is demonstrated at 1.0V-1.5V. Scaling to 0.1 mu m L-gate CMOS is described. At 1.5V, nMOS strong and nominal I-drive=757 and 700 mu A/mu m, and pMOS strong and nominal I-drive=337 and 300 mu A/mu m. For high performance at 1.0V, n- and pMOS are designed with low V-T and higher I-off (100nA/mu m at L-g(min)). At 1V, nMOS strong and nominal I-drive is 516 and 473 mu A/mu m; pMOS strong and nominal I-drive is 220 and 188 mu A/mu m. Benchmarking to FOM and CV/I metrics is performed for this 1.0-1.5V,0.1 mu m node and prior 1.8-1.5V, 0.18 mu m nodes. Present 1.5V, 0.1 mu m CMOS (as well as our recently reported 1.8- 1.5V, 0.18 mu m CMOS) has FOM and CV/I values better than the literature trend. The FOM at V-DD=1.0V (max I-off = 100 nA/mu m) is the same as the 1.5V FOM (max I-off = 1nA/mu m).

引用

页码：223 / 226

页数：4